1. Field of the invention
The present invention relates, in general, to a method for fabricating a semiconductor device applicable for DRAM or ASIC and, more particularly, to a method for fabricating a semiconductor device having a buried channel structure.
2. Description of the Prior Art
In a typical process for FET, an implant which is different in type from the well formed on the surface of a semiconductor device (hereinafter referred to as "counter implant"), is used to form a buried channel at the lower channel region between a source and a drain. Such a buried channel plays the role of controlling the threshold voltage of the resulting FET device, to minimize the short channel effect.
In order to better understand the background of the invention, a description will be given of conventional channel structures, in conjugation with various drawings.
Referring to FIG. 1, a conventional device of buried channel structure is shown. As shown in FIG. 1, an N-type well 2 is formed in the upper region of a P-type semiconductor substrate 1 in a diffusing manner. Then, impurities are implanted in the N-type well 2 to a certain depth, to form a buried channel 3, after which a gate oxide film 4 and a gate 5 are formed in sequence over the N-type well 2, followed by the formation of an oxide film spacer 6 at the side wall of the gate 5. Using the gate 5 and the oxide film spacer 6 as a mask, P-type ions are doped in the N-type well 2, to form a drain/source 7.
Referring to FIG. 2, there is plotted the doped N-type ion densities of the N-well cut through line A-A' of FIG. 1. In this plot, reference symbol "a" represents the N-type ion density within the N well 2 whereas reference symbol "b" stands for the doped ion density in a buried channel converted into P-type and reference symbol "c" for the doped N-type ion density when the buried channel 3 is not formed.
Such formation of a well through diffusion as mentioned above, has a significant problem in that heat treatment is required at a high temperature for an extended period of time.
To overcome this problem, a profiled or retrograde well formation technique, which can bring a significantly improve the performance of the device, has been developed. For example, a buried channel PMOSFET can be created with a counter implant in a semiconductor device having a profiled N well structure. This characteristic can be in described in detail with reference to FIG. 3. FIG. 3 is a plot showing the doped ion densities of the profiled well cut like FIG. 1 (that is, line A-A') in a MOSFET having a buried channel 3 structure.
In the figure, reference symbol "d" represents the doped ion density within the N well 2, reference symbol "e" represents the doped ion density in the area where the buried channel is created, reference symbol "g" represents the doped ion density of the N well 2 located at the lower portion of the buried channel 3 and reference symbol "f" represents the doped ion density in the upper part of the N well 2 when omitting the count implant for the buried channel. It is apparent that the doped ion densities constructed by the profiled or retrograde well technique is much lower than those in the N well constructed through diffusion. In other words, the dose of impurity required for forming the buried channel 3 is lower than that required for forming a well by diffusion.
However, the MOSFET of such a buried channel structure is significantly problematic in that the short channel characteristic is deteriorated because the N type ion density in the region beneath the buried channel is low, as indicated by reference symbol "f".